THERMAL BIAS ANNEALING EXPERIMENTS ON ALUMINUM SILICON-NITRIDE HYDROGENATED AMORPHOUS-SILICON TOP GATE STRUCTURES

Thermal bias annealing experiments have been carried out on aluminum/s ilicon nitride/hydrogenated amorphous silicon top gate structures, and analyzed by quasistatic capacitance measurements. The quasistatic cap acitance versus bias curves always show a well defined minimum which r eflects the minimum in the density of states at the intercept between the conduction band tail and the deep defect distribution. Thermal bia s annealing treatments lend to shifts of the capacitance versus bias c urves of the same sign as the bias-anneal voltage, along with an incre ase of the capacitance minimum. These modifications can be qualitative ly described by changes in the defect densities in the framework of th e defect pool model. However, numerical calculations show that additio nal defects must be introduced to fully and quantitatively account for all experimental data.