HARDWARE STARTING APPROXIMATION METHOD AND ITS APPLICATION TO THE SQUARE-ROOT OPERATION

Quadratically converging algorithms far high-order arithmetic operatio ns typically are accelerated by a starting approximation. The higher t he precision of the starting approximation, the less number of iterati ons required for convergence. Traditional methods have used look-up ta bles or polynomial approximations, or a combination of the two called piecewise linear approximations. This paper provides a revision and ma jor extension to our study [1] proposing a nontraditional method for r eusing the hardware of a multiplier. An approximation is described in the form of partial product array (PPA) composed of Boolean elements. The Boolean elements are chosen such that their sum is a high-precisio n approximation to a high-order arithmetic operation such as square ro ot, reciprocal, division, logarithm, exponential, and trigonometric fu nctions. This paper derives a PPA that produces in the worst case a 16 -bit approximal-ion to the square root operation. The implementation o f the PPA utilizes an existing 53 bit multiplier design requiring appr oximately 1,000 dedicated logic gates of function, additional repoweri ng circuits, and has a latency of one multiplication.