PROGRAMMABLE BIST SPACE COMPACTORS

We address test data compaction for built-in self-test (BIST). We prop ose a novel taxonomy useful for classifying and comparing BIST compact ors. The taxonomy uses the following attributes: space, time, memory, linearity, and circuit (functional) specificity. The thrust of the wor k focuses on BIST space compaction, a process increasingly required wh en a large number of internal circuit nodes need to be monitored durin g test but where area limitations preclude the association of observat ion latches for all the monitored nodes. We introduce a general class of Space compactors denoted as programmable space compactors (PSCs). P rogrammability enables highly-effective space compactors to be designe d for circuits under test (CUT) subjected to a specific set of test pa tterns. Circuit-specific information such as the fault-free and expect ed faulty behavior of a circuit are used to choose PSCs that have bett er fault coverage and/or lower area costs than the commonly-used parit y function. Finding optimal PSCs is a difficult task since the space o f possible PSC functions is extremely large and grows exponentially wi th the number of lines (nodes) to be compacted. We describe an optimiz ation search method based on genetic algorithms for finding combinatio nal PSCs. The factors used to assess the effectiveness of a PSC are it s fault coverage and implementation area. Results reveal that we can f ind PSCs with better fault coverage and cost characteristics than the parity function using modest computing resources, e.g., PSCs with equa l or greater fault coverage than the parity function for as little as 20% of the cost (in terms of gate count) with an investment of only a few hours of workstation computing time.