EXPERIMENTAL OPERATION OF AN RS FLIP-FLOP COMPOSED OF NONLATCHING JOSEPHSON GATES

We present the experimental implementation of an RS flip-flop (RS-FF) composed of de-biased coupled-SQUID (C-SQUID) gates, The C-SQUID gate is a combination of a single-junction SQUID and a double-junction SQUI D. This gate utilizes nonhysteretic Josephson junctions and it is oper ated in nonlatching mode with de-biasing, Several logical functions ar e able to be realized with a C-SQUID gate by adjusting the input bias and the input signal levels, The speed performance of the gate is eval uated by simulation for ring oscillators, and the minimum switching de lay of 6.5 ps/stage is obtained under Josephson critical current densi ty of 10 kA/cm(2). We have fabricated the RS-FF composed of two C-SQUI D NOR gates, The circuit is integrated using a Nb/AlOx/Nb junction tec hnology and its operation is demonstrated experimentally.