HIGH-PERFORMANCE, DEEP-SUBMICRON CMOS TECHNOLOGIES

This paper describes a design method for high-performance, low-voltage operation, and low statistical variation in deep-submicron MOSFETs. T he proposed method features a double side-wall, a counter-doped channe l, and a highly-doped LDD region. Using the highly-doped LDD structure , we obtained a drain current of 0.6 mA/mu m at a supply voltage of 1. 9 V in 0.15 mu m gate-length nMOSFETs. At this voltage, the hot carrie r immunity is around 10 years. Also, a double side-wall, counter-doped pMOSFET structure showed a high immunity against short-channel effect s at a low V-th, resulting in a V-th standard deviation below 20 mV fo r a gate length of 0.1 mu m. The simulated 0.15 mu m gate-length delay for an inverter using experimentally obtained parameters was under 30 ps at 2 V, making it suitable for low-voltage and high-speed operatio n.