TECHNOLOGIES FOR 0.25-MU-M CMOS LOGIC DEVICES

This paper describes a new 0.25 mu m CMOS logic device technology that improves transistor performance and integration density. The technolo gy includes the use of retrograde wells, excimer lithography, a dual-g ate structure, salicide, local interconnects, and self-aligned contact s. Also, a novel gate structure is introduced that is compatible with salicide and self-aligned contacts. The new technology is suitable for fabrication of high-speed transistors and small SRAM cells. Using thi s new technology, we achieved a propagation delay time of 38 ps per st age in an unloaded inverter ring oscillator and an SRAM cell size of 1 0 mu m(2).