PERFORMANCE OPTIMIZATION USING TEMPLATE MAPPING FOR DATAPATH-INTENSIVE HIGH-LEVEL SYNTHESIS

This paper introduces a new approach to performance-driven template na pping for high-level synthesis, Template mapping, the process of mappi ng high-level algorithmic descriptions to specialized hardware librari es or instruction sets, involves template matching, template selection , and clock selection. Efficient algorithms for each are presented, an d novel issues such as partial matching are addressed. The paper focus es on datapath-intensive ASIC design, though the concepts are also hig hly applicable to compiler development. Experimental results on exampl es from real applications show significant improvements in throughput with limited area overhead.