AUTOMATION OF IC LAYOUT WITH ANALOG CONSTRAINTS

A methodology for the automatic synthesis of full-custom IC layout wit h analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise, infeasib ility is detected as soon as possible, thus providing a robust and eff icient design environment. Zn the proposed approach, performance speci fications are translated into lower-level bounds on parasitics or geom etric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement , routing, and compaction. For each tool, a detailed description is pr ovided of its functionality, of the way constraints are mapped and enf orced, and of its impact on the design flow. Examples drawn from indus trial applications are reported to illustrate the effectiveness of the approach.