ANALYTIC MODELING OF CACHE COHERENCE BASED PARALLEL COMPUTERS

In this paper, we propose an analytic model using a semi-markov proces s for parallel computers which provides hardware support for a cache c oherence mechanism. The model proposed here, the Semi-markov Memory an d Cache coherence Interference model, can be used for the performance prediction of cache coherence based parallel computers since it can be easily applied to descriptions of the waiting states due to network c ontention or memory interference of both normal data accesses and cach e coherence requests. Conventional analytic models using stochastic pr ocesses to describe parallel computers have the problem of numerical e xplosion in the number of states necessary as the system size increase s even for simple parallel computers without cache coherence mechanism s. The number of states required by constructing our proposing analyti c model, however, does not depend on the system size but only on the k ind of cache coherence protocol. For example, the number of states for the Synapse cache coherence protocol is only 20, as is described in t his paper. Using the proposed analytic model, we investigate several c omparative experiments with widely known simulation results. We found that there is only a 7.08 % difference between the simulation and our analytic model, while our analytic model can predict the performance o f a 1,024 processor system in the order of microseconds.