A 2.5-GB S 15-MW CLOCK RECOVERY CIRCUIT

This paper describes the design of a 2.5-Gb/s 15-mW clock recovery cir cuit based on the quadricorrelator architecture. Employing both phase and frequency detection, the circuit combines high-speed operations su ch as differentiation, full-wave rectification, and mixing in one stag e to lower the power dissipation. In addition, a two-stage voltage-con trolled oscillator is utilized that incorporates both phase shift elem ents to pro,ide a wide tuning range and isolation techniques to suppre ss the feedthrough due to input data transitions, Fabricated in a 20-G Hz 1-mu m BiCMOS technology, the circuit exhibits an rms jitter of 9.5 ps and a capture range of 300 MHz.