AN 80-MOPS-PEAK HIGH-SPEED AND LOW-POWER-CONSUMPTION 16-B DIGITAL SIGNAL PROCESSOR

This paper describes a 16-b fixed point digital signal processor (DSP) , especially its multiply-accumulate (MAC) unit, memories, and instruc tion set, By adopting a redundant binary multiplier and a variable pip eline structure, this DSP's MAC unit, compared to a conventional MAC u nit, consumes about 15% less power and operates 24% faster, Furthermor e, its double-speed MAC mechanism can realize twice the performance of a single MAC operation while consuming only 69% more power, By being able to more finely control which portions of memory are activated, th e data ROM and data RAM's precharge current was reduced to about 1/8 o f the conventional ROM and RAM's, We redesigned the instruction set an d reduced its width from 32 b to 24 b based on the analysis of data ge nerated by simulating an application program on our previous DSP. The reduction in instruction width made our on-chip instruction memory siz e 33% smaller than the previous one, This chip is fabricated with a 0. 5-mu m double-metal-layer CMOS process and achieves 80-MOPS-peak doubl e speed multiply-accumulate performance.