Efficient charge recovery logic (ECRL) is proposed as a candidate for
low-energy adiabatic logic circuit. Power comparison with other logic
circuits is performed on an inverter chain and a carry lookahead adder
(CLA). ECRL CLA is designed as a pipelined structure for obtaining th
e same throughput as a conventional static CMOS CLA. Proposed logic sh
ows four to six times power reduction with a practical loading and ope
ration frequency range. An inductor-based supply clock generation circ
uit is proposed. Circuits are designed using 1.0-mu m CMOS technology
with a reduced threshold voltage of 0.2 V.