FAULT-TOLERANT DESIGNS FOR 256 MB DRAM

This paper describes fault-tolerant designs, which have been used to b oost the yield of a 286 mm(2) 256 Mb DRAM with x32 both-ends DQ, The 2 56 Mb DRAM consists of sixteen 16 Mb units, each containing one 128 Kb row redundancy block, This row redundancy block architecture allows f lexible row redundancy replacement, where random faults, clustered fau lts, and grouped faults can be efficiently repaired, Flexible column r edundancy replacement with interchangeable master DQ's (MDQ) is used t o allow a 256 b data compression without causing a data conflict, whil e improving the column access speed by 2 ns. A depletion NMOS bitline- precharge-current-limiter suppresses the current flow which occurs as a result of a wordline-bitline short-circuit to only 15 mu A per cross fail, avoiding a standby current fail, Consequently, the hardware res ults show a significant yield enhancement of 16 times relative to the intrablock/segment replacement, Detailed simulation results show that this 256 Mb DRAM allows 275 random faults to be repaired with 5.5% sil icon area overhead for 80% chip yield.