SOI-DRAM CIRCUIT TECHNOLOGIES FOR LOW-POWER HIGH-SPEED MULTIGIGA SCALE MEMORIES

This paper describes a silicon on insulator (SOI) DRAM which has a bod y bias controlling technique for high-speed circuit operation and a ne w type of redundancy for low standby power operation, aimed at high yi eld, The body bias controlling technique contributes to super-body syn chronous sensing and body-bias controlled logic. The super-body synchr onous sensing achieves 3.0 ns faster sensing than body synchronous sen sing and the body-bias controlled logic realizes 8.0 ns faster periphe ral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM, The body-bias controlled logic also realiz es a body-bias change current reduction of 1/20, compared with a bulk well-structure, A new type of redundancy that overcomes the standby cu rrent failure resulting from a wordline-bitline short is also discusse d in respect of yield and area penalty.