PGEN - A NOVEL-APPROACH TO SEQUENTIAL-CIRCUIT TEST-GENERATION

A novel approach, called PGEN, is proposed to generate test patterns f or resettable or nonresettable synchronous sequential circuits, PGEN c ontains two major routines, Sequential PODEM (S-PODEM) and a different ial fault simulator. Given a fault, S-PODEM uses the concept of multip le time compression supported by a pulsating model, and generates a te st vector in a single (yet compressed) time frame. Logic simulation (i ncluded in S-PODEM) is invoked to expand the single test vector into a test sequence. The single test vector generation methodology and logi c simulation are well coordinated and significantly facilitate sequent ial circuit test generation, A modified version of differential fault simulation is also implemented and included in PGEN to cover other fau lts detected by the expanded test sequence. Experiments using computer simulation have been conducted, and results are quite satisfactory.