FAULT MODELING OF ECL FOR HIGH FAULT COVERAGE OF PHYSICAL DEFECTS

Bipolar Emitter Coupled Logic (ECL) devices can now be fabricated at h igher densities and consumes much lower power, Behaviour of simple and complex ECL gates are examined in the presence of physical faults. Th e effectiveness of the classical stuck-at model in representing physic al failures in ECL gates is examined. It is shown that the conventiona l stuck-at fault model cannot represent a majority of circuit level fa ults, A new augmented stuck-at fault model is presented which provides a significantly higher coverage of physical failures, The model may b e applicable to other logic families that use logic gates with both tr ue and complementary outputs. A design for testability approach is sug gested for on-line detection of certain error conditions occurring in gates with true and complementary outputs which is a normal implementa tion for ECL devices.