ANALYSIS OF A CONTROL MECHANISM FOR A VARIABLE-SPEED PROCESSOR

One limitation on the operating speed of electronic circuits is the ra te at which the packaging can dissipate heat. In CMOS technology, the heat generated by a processor is approximately proportional to its clo ck rate. This paper examines the idea of using a variable-speed proces sor (VSP) that can be operated at a high clock speed, and then slowed down to a lower speed before heat accumulation destroys the circuit. U nder a workload consisting of bursts of work alternating with idle per iods (corresponding to cache misses or other delays), this results in a higher average operating speed. This paper shows the optimality of a bang-bang control for the clock rate. It also examines an easier-to-i mplement policy that estimates the junction temperature through an upp er bound, and uses this to control the clock rate. Closed-form express ions are derived for the mean rate of instructions executed by a VSP u sing each control method. Numerical studies show that both policies gi ve substantial improvements in performance over a single speed process or. Furthermore, the studies suggest that a VSP with a maximum clock r ate of 2-4 times that of the single speed processor would suffice to o btain the bulk of the performance improvement. In many cases, the aver age throughput gain is on the order of 40-60%, without exceeding therm al limits.