DYNAMIC DATA RETENTION AND IMPLIED DESIGN CRITERIA FOR FLOATING-BODY SOI DRAM

Authors
SUH D FOSSUM JG PELELLA MM
Citation
D. Suh et al., DYNAMIC DATA RETENTION AND IMPLIED DESIGN CRITERIA FOR FLOATING-BODY SOI DRAM, IEEE electron device letters, 17(8), 1996, pp. 385-387
Citations number
8
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE electron device letters → ACNP
ISSN journal
07413106
Volume
17
Issue
8
Year of publication
1996
Pages
385 - 387
Database
ISI
SICI code
0741-3106(1996)17:8<385:DDRAID>2.0.ZU;2-9
Abstract
A physical MOSFET model in SOISPICE is used to characterize dynamic da ta retention in PD/SOI DRAM cells. Simulations show that transient par asitic BJT current underlies peculiar data retention, and they suggest how periodic body discharge effected by data refresh with a high flat band-voltage cell transistor can render PD/SOI technology viable and a ttractive for gigabit DRAM applications.