TIMING VERIFICATION SYSTEM FOR RELAY CIRCUIT BEHAVIORS

A timing verification system for analogue relay circuits has been deve loped. The verification is performed by Time-Symbolic Logic (TSL) simu lation that allows symbolic representation of the time. With represent ation of the relay actuation time by time-variables, TSL simulation ca n simulate all possible behaviors that differ with the timing of relay action. To reduce the simulation cost, the simulation technique was i mproved using the characteristics of the relay circuits. Users can ver ify the circuit behavior without preparing numerous simulation inputs or executing numerous simulation cases. The developed system was appli ed to the verification of actual circuits. The circuit behaviors with all the possible timings under the realistic constraints were simulate d and verified. These application studies confirmed that the developed system is useful and effective.