The architecture presented combines a cross-coupled 'winner takes all'
circuit with a multi-input digital latch. Only one of the digital out
puts is a logic 'one', corresponding to the largest analogue input. A
five-input prototype was built using a 2 mu m CMOS process. The 300 x
280 mu m(2) circuit dissipates 1mW from a single 5V supply at a maximu
m clock frequency of 10MHz.