GALLIUM-ARSENIDE PSEUDODYNAMIC LATCHED LOGIC

Citation
Jf. Lopez et al., GALLIUM-ARSENIDE PSEUDODYNAMIC LATCHED LOGIC, Electronics Letters, 32(15), 1996, pp. 1353-1354
Citations number
7
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
ISSN journal
00135194
Volume
32
Issue
15
Year of publication
1996
Pages
1353 - 1354
Database
ISI
SICI code
0013-5194(1996)32:15<1353:GPLL>2.0.ZU;2-L
Abstract
A new GaAs logic family, pseudo-dynamic latched logic (PDLL), is intro duced. Compared with traditional static GaAs logic families, PDLL allo ws complex gate design with less power dissipation. In addition, it ov ercomes problems associated with charge degradation in the storage nod es in dynamic logic gates, and operates at relatively high temperature s. PDLL is self-latched which leads iu the possibility of implementing compact pipeline systems.