DESIGN OF A PROCESSOR ELEMENT FOR A HIGH-PERFORMANCE MASSIVELY-PARALLEL SIMD SYSTEM

This paper describes the architecture of the General Purpose with Floa ting Point support (GPFP) processing element, which uses the expansion of circuitry from VLSI advances to provide on-chip memory and cost-ef fective extra functionality. A major goal was to accelerate floating p oint arithmetic. This was combined with architectural aims of cost-eff ectiveness, achieving the floating-point capability from general-purpo se units, and retaining the 1-bit manipulations available in the earli er generation. With a 50 MHz clock each PE is capable of 2.5 MegaFlops . Normalized to the same clock rate, the GPFP PE exceeds first generat ion PEs by far, namely the DAP by a factor of 50 and the MPP by a fact or of 20, and also outperforms the recent MasPar design by a factor of four. A 32 x 32 GPFP array is capable of up to 2.5 GigaFlops and 6500 MIPS, on 32-bit additions. These speedups are obtained by architectur al features rather than increased width of data-handling and are combi ned with parsimonious use of circuitry compatible with massively paral lel fabrication. The GPFP also incorporates Reconfigurable Local Contr ol (RLC), a technique that combines a considerable degree of local aut onomy within PEs and microcode flexibility, giving the machine improve d general-purpose programmability in addition to floating-point numeri cal performance.