INTERCONNECT PROPAGATION DELAY MODELING AND VALIDATION FOR THE 16-MB CMOS SRAM CHIP

In this paper, a closed-form expression for complementary metal-oxide semiconductor (CMOS) static random access memory component (SRAM) chip propagation delay is developed, This allows accurate calculation of t he signal propagation delay of multilayer interconnects within the CMO S SRAM chip and also takes into account the delay of the CMOS SRAM cel ls driving the branched transmission line and the driving SRAM cell lo ading aspects of the interconnect line, Simulation results are present ed to show the accuracy and efficiency of the propagation delay model, A case study of 16 MB CMOS SRAM chip performance evaluation is presen ted, The proposed closed-form delay expression results in an absolute maximum error smaller than 4.8% in comparison to the measured data, Th e proposed closed-form expression can be used for various highspeed, h igh-density multilayer interconnect SRAM's, dynamic random access memo ries (DRAM's), FPGA's, and application-specific integrated circuits (A SIC's).