FULL-WAVE ANALYSIS OF TRANSMISSION-LINES IN A MULTILAYER SUBSTRATE WITH HEAVY DIELECTRIC LOSSES

The worldwide CMOS integrated circuits industry relies on heavily dope d silicon wafers as the starting material for chip fabrication; the re sulting integrated circuits are confined to the upper few microns of t he wafer, which itself Is as much as 600-mu m thick. These heavily dop ed silicon substrates are not insulators, but are actually very lossy; a loss tangent of 10(5) at 1 MHz is a fairly typical characteristic o f the wafers. Although it is becoming increasingly necessary to model accurately the currents which flow between transistors and interconnec ts into the substrates, existing computer-aided design (CAD) simulatio n packages fail to provide accurate results in modeling such heavy die lectric losses, because most CAD packages rely on small perturbation m ethods in the analysis of dielectric losses. In this paper, the proble m of computing the electrical behavior of lossy dielectrics is analyze d by the full wave method, and the mutual capacitances of transmission lines;above such heavily doped CMOS substrates are computed and compa red with laboratory experimental measurements. Good agreement between analytical and measurement results has been obtained.