CIRCUIT PLACEMENT, CHIP OPTIMIZATION, AND WIRE ROUTING FOR IBM IC TECHNOLOGY

Recent advances in integrated circuit technology have imposed new requ irements on the chip physical design process. At the same time that pe rformance requirements are increasing, the effects of wiring on delay are becoming more significant. Larger chips are also increasing the ch ip wiring demand, and the ability to efficiently process these large c hips in reasonable time and space requires new capabilities from the p hysical design tools. Circuit placement is done using algorithms which have been used within IBM for many years, with enhancements as requir ed to support additional technologies and larger data volumes. To meet timing requirements, placement may be run iteratively using successiv ely refined timing-derived constraints. Chip optimization tools are us ed to physically optimize the clock trees and scan connections, both t o improve clock skew and to improve wirability. These tools interchang e sinks of equivalent nets, move and create parallel copies of clock b uffers, add load circuits to balance clock net loads, and generate bal anced clock tree routes. Routing is done using a grid-based, technolog y-independent router that has been used over the years to wire chips. There are numerous user controls for specifying router behavior in par ticular areas and on particular interconnection levels, as well as adj acency restrictions.