POWERPC AS A10 64-BIT RISC MICROPROCESSOR

The PowerPC AS(TM) A10 64-bit RISC microprocessor is a 4.7-million-tra nsistor integrated circuit design, using IBM CMOS 5L 0.5-mu m, 3-V, fo ur-level-metal ASIC technology, Support for the PowerPC AS architectur e is implemented in a 213-mm(2) die using a semicustom design methodol ogy, Chip density and speed are enhanced through the use of custom mac ros and multiport arrays, An on-chip phase-locked-loop circuit is used to reduce chip-to-chip clock skew, Full utilization of the four-level -metal interconnect technology was achieved through architectural floo rplanning, performance clustering, and timing-driven placement and wir ing, with a total wire length of over 102 meters placed on the 14.6 x 14.6-mm die, The microprocessor is a pipelined, superscalar design wit h five separate functional units, a 4KB instruction cache, and an 8KB data cache, The design includes parity, error-correction, and error-lo gging functions, as well as self-test for logic and arrays during powe r-on, The design is robust and implements a wide range of performance configurations at the system level, allowing direct attachment of DRAM to the processor, or high-performance L2 cache options using high-spe ed SRAM, An on-chip system I/O bus and bus controller are provided for attachment of peripherals.