ISSUES IN THE DESIGN OF HIGH-PERFORMANCE SIMD ARCHITECTURES

In this paper, we consider the design of high performance SIMD archite ctures. We examine three mechanisms by which the performance of this c lass of machines may be improved, and which have been largely unexplor ed by the SIMD community. The mechanisms are pipelined instruction bro adcast, pipelining of the PE architecture, and the introduction of a n ovel memory hierarchy in the PE address space which we denote the dire ct only data cache, (dod-cache). For each of the performance improveme nts, we develop analytical models of the potential speedup, and apply those models to real program traces obtained on a MasPar MP-2 system. In addition we consider the impact of all improvements taken together.