A 29-NS 64-MB DRAM WITH HIERARCHICAL ARRAY ARCHITECTURE

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architec ture has been developed, For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme , To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers a re distributed in the array, To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted, A hierarchic al I/O scheme with semidirect sensing switch is introduced for high sp eed data transfer in the I/O paths. By combining these proposed circui t techniques and 0.25-mu m CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71 x 1.20 mu m(2), and the chip size is 15.91 x 9.06 mm(2). A typical access time under 3.3 V power su pply voltage is 29 ns.