DESIGN FOR VELOCITY SATURATED, SHORT-CHANNEL CMOS DRIVERS WITH SIMULTANEOUS SWITCHING NOISE AND SWITCHING TIME CONSIDERATIONS

Design guidelines for velocity-saturated, short-channel CMOS drivers a re presented in this paper based on approximating the package inductan ce by an effective, lumped, power-supply bus parasitic inductance. A w orst-case maximum simultaneous switching noise V-GM and gate propagati on delay time t(D,1/2) are treated as performance constraints for whic h driver design tradeoffs between driver geometry, the maximum number of simultaneously switched drivers, and the effective inductance are o btained, For typical loading conditions, design examples based on the proposed guidelines are shown by SPICE simulations using the MOS3 mode l to agree with both design goals within 10%.