T. Douseki et S. Mutoh, A 1-V MTCMOS CIRCUIT HARDENDED TO TEMPERATURE-DEPENDENT DELAY-TIME VARIATION, IEICE transactions on electronics, E79C(8), 1996, pp. 1131-1136
This paper describes the effects of operating temperature on delay tim
e in a 1-V multi-threshold CMOS (MTCMOS) circuit. Delay-time analysis
including the temperature factor shows that the delay-time variation o
f the CMOS circuit becomes small for low-voltage operation and the var
iation is mainly determined by the threshold voltage and its variation
-rate with temperature. As a design method of a MTCMOS circuit with bo
th high-threshold and low-threshold MOSFETs, optimization of the low-t
hreshold voltage at which the delay-time of the circuit is independent
of operating temperature is described in detail. The validity of the
design method is confirmed by the evaluation of a gate-chain TEG and a
1-V 12 K-gate digital-filter LSI fabricated with 0.5-mu m MTCMOS tech
nology.