PARALLEL PIXEL PROCESSING USING PROGRAMMABLE GATE ARRAYS

Authors
BUDGETT DM TANG PE SHARP JH CHATWIN CR YOUNG RCD WANG RK SCOTT BF
Citation
Dm. Budgett et al., PARALLEL PIXEL PROCESSING USING PROGRAMMABLE GATE ARRAYS, Electronics Letters, 32(17), 1996, pp. 1557-1559
Citations number
2
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
32
Issue
17
Year of publication
1996
Pages
1557 - 1559
Database
ISI
SICI code
0013-5194(1996)32:17<1557:PPPUPG>2.0.ZU;2-7
Abstract
A reconfigurable hardware design permits very fast feature extraction from high frame rate video images. By implementing parallel pixel proc essing paths in programmable gate arrays, a wide range of image proces sing algorithms can be implemented in realtime.