SOURCE AND DRAIN PARASITIC RESISTANCES OF AMORPHOUS-SILICON TRANSISTORS - COMPARISON BETWEEN TOP NITRIDE AND BOTTOM NITRIDE CONFIGURATIONS

The source and drain parasitic resistances of amorphous silicon based thin film transistors (aSi:H TFT) are investigated using a very simple TFT model including a parameter extraction method. We show that this method provides an accurate measurement of these resistances and clear ly explains their influence on the apparent field effect mobility mu(a ) of the TFTs. We compare the parasitic resistances of TFTs for the to p nitride (TN) and bottom nitride (BN) configurations and we show that the usual different performances observed on the two configurations c an be mainly attributed to the differences in the parasitic resistance s.