ITA - AN ALGORITHM FOR I-DDQ TESTABILITY ANALYSIS

This paper presents the I-DDQ Testability Analysis (ITA) algorithm for the estimation of a circuit design's leakage fault testability. The a lgorithm is based on the calculation of the probability of applying ea ch of a set of ''essential vectors'' to each gate in the circuit. The essential vectors for each gate represent the minimal vector set that provides maximal leakage fault coverage.ITA assumes independence of ci rcuit net values, except in the case of reconvergent fanout. Reconverg ent fanout is identified by ''levelizing'' the circuit and propagating sets of labels from the primary inputs forward through the circuit, b eginning with unique labels (integers) on each primary input. ITA eval uation of reconvergent fanout points then uses a backward implication procedure to calculate the essential vector probability values for the reconvergent gate, except in the case where backward implication is n ot deterministic. Results of an implementation of ITA are presented fo r a set of benchmark circuits, including a sample of the ISCAS '85 and '89 circuits.