INTERFACE PROPERTIES OF SI3N4 SI/N-GAAS METAL-INSULATOR-SEMICONDUCTORSTRUCTURE USING A SI INTERLAYER/

We report the effects of Si interlayer on the capacitance-voltage (C-V ) characteristics of Si3N4/Si/n-GaAs metal-insulator-semiconductor (MI S) capacitor as a function of interfacial Si thickness, Si growth temp erature and post-growth annealing. The thickness of interfacial Si was found to be the most pivotal parameter for the best interface propert ies as determined by the comprehensive C-V and conductance measurement s. The minimum interface trap density D-it of 5 x 10(10) eV(-1) cm(-2) near midgap is realized with a Si interlayer of 10 Angstrom. The hyst eresis and frequency dispersion of the GaAs MIS capacitor were lower t han 50 mV, and some of them as low as 30 mV under a field swing of abo ut +/-1.3 MV cm(-1). Ex-situ solid-phase annealing (SPA) at 550 degree s C in N-2 using rapid thermal annealing was sufficient to recrystalli ze the as-deposited Si interlayer at a low temperature (less than 400 degrees C). The minimum D-it thus obtained using ex-situ SPA was less than 1.5 x 10(11) eV(-1) cm(-2) regardless of Si deposition temperatur e. 1 MHz frequency response at 80 K requires that the traps be within 35 meV of the conduction band of GaAs. The effects of SPA and post-gro wth annealing on the interface stability are also discussed.