A METHODOLOGY FOR THE RAPID INJECTION OF TRANSIENT HARDWARE ERRORS

Ultra-dependable computing demands Verification of fault-tolerant mech anisms in the hardware. The most popular class of verification methodo logies, fault-injection, is fraught with a host of limitations. Method s which are rapid enough to be feasible are not based on actual hardwa re faults. On the other hand, methods which are based on gate-level fa ults require enormous time resources. This research tries to bridge th at gap by developing a new fault-injection methodology for processors based on a register-transfer-language (RTL) fault model. The fault mod el is developed by abstracting the effects of low-level faults to the RTL level. This process attempts to be independent of implementation d etails without sacrificing coverage, the proportion of errors generate d by gate-level faults that are successfully reproduced by the RTL fau lt model. A prototype tool, ASPHALT, is described which automates the process of generating the error patterns. The IBM RISC-Oriented Micro- Processor (ROMP) is used as a basis for experimentation. Over 1.5 mill ion transient faults are injected using a gate-level model. Over 97% o f these are reproduced with the RTL model at a speedup factor of over 500:1. These results show that the RTL fault model may be used to grea tly accelerate fault-injection experiments without sacrificing accurac y.