AUGMENTED BINARY HYPERCUBE - A NEW ARCHITECTURE FOR PROCESSOR MANAGEMENT

Citation
H. Lalgudi et al., AUGMENTED BINARY HYPERCUBE - A NEW ARCHITECTURE FOR PROCESSOR MANAGEMENT, I.E.E.E. transactions on computers, 45(8), 1996, pp. 980-984
Citations number
11
Categorie Soggetti
Computer Sciences","Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture
ISSN journal
00189340
Volume
45
Issue
8
Year of publication
1996
Pages
980 - 984
Database
ISI
SICI code
0018-9340(1996)45:8<980:ABH-AN>2.0.ZU;2-8
Abstract
Augmented Binary Hypercube (AH) architecture consists of the binary hy percube processor nodes (PNs) and a hierarchy of management nodes (MNs ). Several distributed algorithms maintain subcube information at the MNs to realize fault tolerant, fragmentation free processor allocation and load balancing. For efficient implementation of AH, we map MNs on to PNs, define and prove infeasibility of ideal mappings. We propose e asily implementable nonoptimal mappings, having negligible overheads o n performance. Extensive simulation studies and performance analysis c onclude that these algorithms realize significantly better average job completion time and higher processor utilization, as compared to the best sequential allocation schemes and parallel implementation of Free List [7]. AH algorithms can be tuned or adapt to the job and system c haracteristics, and resource management traffic.