A 28 MW 16-BIT DIGITAL SIGNAL PROCESSOR FOR THE PDC HALF-RATE CODEC

A low power consumption 16-bit fixed point Digital Signal Processor (D SP) has been developed to realize a half-rate CODEC for the Personal D igital Cellular (PDC) system. Dual datapath architecture has been empl oyed to execute multiply-accumulate (MAC) operations with a high degre e of efficiency. With this architecture, 86.3% of total MAC operations in the Pitch Synchronous Innovation Code Excited Linear Prediction (P SI-CELP) program are executed in parallel, so that total instruction c ycles are reduced by 23.1%. The area overhead for the dual datapath ar chitecture is only 3.0% of the total area. Furthermore, in order to re duce power consumption, circuit design techniques are also extensively applied to RAMs, ROMs, and crock circuits, which consume the great ma jority of power. By reducing the number of precharging bit lines, a po wer reduction of 49.8% is achieved in RAMs, and above 40% in ROMs. By applying gated clock to clock lines, a power reduction of 5.0% is achi eved in the DSP that performs the PSI-CELP algorithm. The DSP is fabri cated in 0.5 mu m single-poly, double-metal CMOS technology. The PSI-C ELP algorithm for the PDC half-rate CODEC can operate at 22.5 MHz inst ruction frequency and 1.6 V supply voltage, resulting in a low-power c onsumption of 28 mW.