A 250 MV BIT-LINE SWING SCHEME FOR 1-V OPERATING GIGABIT SCALE DRAMS

This paper proposes a small 1/4 Vcc bit-line swing scheme and a relate d sense amplifier scheme for low power 1 V operating DRAM. Using the p roposed small bit-line swing scheme, the stress bias of memory cell tr ansistor and capacitor is reduced to half that of the conventional DRA M, resulting in improvement of device reliability. The proposed sense amplifier scheme achieves high speed and stable sensing/restoring oper ation at 250mV bit-line swing, which is much smaller than threshold vo ltage. The proposed scheme reduces the total power dissipation of bit- line sensing/restoring operation to 40% of the conventional one. This paper also proposes a small 4F(2) size memory cell and a new twisted b it-line scheme. The array noise is reduced to 8.6% of the conventional DRAM.