SHEET RESISTANCE AND LAYOUT EFFECTS IN ACCELERATED TESTS FOR DIELECTRIC RELIABILITY EVALUATION

Different extrapolation algorithms can be used to calculate gate oxide lifetime from accelerated reliability tests. The measurement is often carried out on large area capacitors in order to be statistically mea ningful with respect to the active oxide area of the devices. This als o allows a reduction of test time and therefore of cost. However, both the capacitor layout and the sheet resistance either of gate or of su bstrate or of interconnections can have a huge impact on the correctne ss of the experimental data. In this work it will be shown that lifeti me forecast can be largely overestimated due to series resistance. Mor eover, a non-optimized layout of the capacitor can induce a non-unifor m stress on the oxide due to sheet resistance effects. The validity of the accelerated test is also questionable in this case. Some guidelin es to avoid errors in the collection of raw data will also be given. C opyright (C) 1996 Elsevier Science Ltd.