ENERGY RECOVERY CIRCUITS USING REVERSIBLE AND PARTIALLY REVERSIBLE LOGIC

This paper presents a new family of logic gates for low energy computi ng using pulsed power CMOS logic. The logic gates use the principles o f adiabatic switching and results show that in typical cases 90% of th e energy can be recovered with operating frequency around 1 MHz. Const ant capacitance condition is enforced in our designs so that signals' energy can be efficiently recycled in the chip, We also present a deta iled analysis and modelling of energy dissipation in adiabatic circuit s. The models were experimentally validated using the circuit simulato r SPICE, A simplified version of adiabatic logic with simplicity compa rable to static CMOS circuits is also presented, For a 2 x 2 multiplie r using this type of logic, 60% of energy can be saved over static CMO S case at 20 MHz and there is 35% less energy consumption at 100 MHz.