MEMORY SHARING PROCESSOR ARRAY (MSPA) ARCHITECTURE

In this paper, a design of a new processor array architecture with eff ective data storage schemes which meets the practical requirement of a reduced number of processor elements is proposed. Its design method i s shown to be drastically simpler than the popular systolic arrays. Th is processor array which we call Memory Sharing Processor Array (MSPA) consists of a processor array, several memory units, and some address generation hardware units used to minimize the number of I/O parts. M SPA architecture with its design methodology tries to overcome overlap ping data storages, idle processing time and I/O bottleneck problems, which mostly degrade the performance of systolic architecture. It has practical advantages over the systolic array in the clew of area-effic iency, high throughput and practical input schemes.