AREA-EFFICIENT MULTIPLIERS FOR DIGITAL SIGNAL-PROCESSING APPLICATIONS

An area-efficient parallel sign-magnitude multiplier that receives two N-bit numbers and produces an N-bit product, referred to as a truncat ed multiplier, is described, The quantization of the product to N bits is achieved by omitting about half the adder cells needed to add the partial products but in order to keep the quantization error to a mini mum, probabilistic biases are obtained and are then fed to the inputs of the retained adder cells, The truncated multiplier requires approxi mately 50% of the area of a standard parallel multiplier. The paper th en shows that this design strategy can also be applied for the design of two's-complement multipliers. The paper concludes with the applicat ion of the truncated multiplier for the implementation of a digital fi lter and it is shown that the signal-to-noise ratio of the digital fil ter using a truncated multiplier is better than that using a standard multiplier.