An STM-4 rate serial data transmitter (SDT) is implemented using a 0.8
mu m CMOS process. The charge injection method is adopted for the del
ay cells in the VCO to enhance the oscillation frequency. By optimizin
g the combination of NOR gates in the shift register, the delay of the
data serializer is reduced. Probable timing errors are avoided by pha
se reversal of the serial data clock. It dissipates about 700 mW at 62
4 Mbps.