A MONOLITHIC OPTOELECTRONIC RECEIVER IN STANDARD 0.7-MU-M CMOS OPERATING AT 180 MHZ AND 176-FJ LIGHT INPUT ENERGY

A novel monolithic optoelectronic receiver/converter system is present ed in standard 0.7-mu m N-well CMOS technology. Differential light inp ut incident on enlarged drains of two MOS transistors of a sense ampli fier induces latching in either the digital HIGH state or the digital LOW state. The enlarged drains serve as photodiodes, circumventing hyb ridization techniques like flip-chip and/or solderbumping necessary wh en using III-V photodiodes. The first receivers of this type have phot odetector areas of 15 x 15 mu m(2) and demonstrate bitrates of 180 Mb/ s with a differential light input of 176 fJ. The electrical power diss ipation is of the order of the dissipation of one CMOS logic gate. The very small total receiver area makes the receiver further perfectly s uited for use in massive parallel optical interconnects between VLSI c hips.