VERTICAL 100 NM SI-P CHANNEL JFET GROWN BY SELECTIVE EPITAXY

We have fabricated a vertical silicon junction field-effect transistor (JFET) with a SiO2/polysilicon/SiO2 gate structure. Due to the vertic al structure the polysilicon gate length can be easily controlled in t he sub-100 nm region. The SiO2, layers below and above the gate reduce the gate-drain and gate-source capacitance due to the relatively low dielectric constant of the SiO2 in addition the SiO2 above the gate st ructure allows the use of selective epitaxy. The channel length of the devices was varied from 0.6 mu m down to 0.3 mu m leading to an impro vement of the transconductance and output conductance. A transconducta nce of 51 mS/mm was achieved for a channel length of 0.4 mu m.