A VLSI ARCHITECTURE OF THE TRELLIS DECODER BLOCK FOR THE DIGITAL HDTVGRAND ALLIANCE SYSTEM

This paper describes the design of a VLSI architecture fm the trellis decoder block on a single-chip FEC (Forward Error Correction) decoder supporting both the 8 VSB terrestrial broadcast mode and the 16 VSB hi gh data-rate mode for cable proposed by the Digital HDTV Grand Allianc e (GA). The trellis decoder block consists of 12 trellis decoders, eac h of which is designed for the GA 8 VSB mode. lit the proposed archite cture, a unique branch metric unit is devised and employed for both th e additive-white-Gaussian-noise (AWGN) channel and the 1-D partial res ponse channel. This makes the implementation complexity of the propose d trellis decoder much the same as that of a usual 8-state trellis dec oder. The proposed trellis decoder works as the partial response trell is decoder when the NTSC rejection filter is activated to reduce the N TSC cochannel interference, while if works as the optimal trellis deco der when there is little or no NTSC interference.