In a digital VCR, DCT/IDCT is performed by both 8x8 mode and 2x4x8 mod
e to improve coding efficiency, In this paper, a new 2-D DCT/IDCT proc
essor which requires minimal hardware overhead for 8x8/2x4x8 mode chan
ge for digital VCR is presented. The proposed DCT/IDCT processor uses
a concurrent architecture and executes both DCT and IDCT with 8x8 and
2x4x8 mode selection. This chip is implemented on the basis of the row
-column decomposition scheme. The proposed architecture minimizes hard
ware overhead for 2x4x8 mode by sharing the same datapath with 8x8 mod
e as much as possible. The proposed architecture also reduces the hard
ware and the chip size by exploiting the table look-up method instead
of the extra multiplication circuits in the weighting coefficients han
dling. The implemented DCT/lDCT processor satisfies the accuracy speci
fication of digital VCR.