STRUCTURE AND PERFORMANCE OF A NEW DATA CLOCK TIME RECOVERY PHASE-LOCKED LOOP

A new phase locked loop (PLL)-based data clock recovery circuit having non-linear error control characteristics has been proposed. Its perfo rmance has been studied by analytical means, by numerically solving th e system eqution using computer, and by hardware experiment in the rad io frequency band. Different performance-measuring parameters of the s ystem such as acquisition range and transient response time obtained b y different methods confirm the improved response of the proposed circ uit compared to the conventional system.