CAA DECODER FOR CELLULAR-AUTOMATA BASED BYTE ERROR-CORRECTING CODE

Design of Cellular Automata (CA) based byte error correcting code anal ogous to extended Reed-Solomon code has been proposed in [1], [2]. Thi s code has same restrictions on error correction as that of extended R -S code. In this paper a new design scheme has been reported for paral lel implementation of CA based SbEC/DbED and DbEC/DbED code that is an alogous to the conventional R-S code. Both the encoder and decoder of this code can be efficiently implemented with an array of CA (CAA) wit h high throughput. The design is ideally suited for high speed memory systems built with byte organized RAM chips. Extension of the scheme t o detect/correct larger number of byte errors has also been reported. Throughput of the decoder to handle t byte errors (t less than or equa l to 4) can be found to be substantially better than that of conventio nal R-S decoder. The proposed decoder provides a simple, modular and c ost effective design that ideally suits for VLSI implementation.