EASILY MANUFACTURABLE SHALLOW TRENCH ISOLATION FOR GIGABIT DYNAMIC RANDOM-ACCESS MEMORY

A simple and easily manufacturable shallow trench isolation (STI) proc ess is developed for 1 Gbit dynamic random access memory (DRAM) and po ssibly DRAMs with ever greater capacity. The main features of this STI scheme are dual slope trench formation and selective dry-etching-assi sted chemical mechanical polishing (CMP) planarization. The dual slope trench is formed by utilizing polymer generation during trench etchin g to improve the sub-threshold conduction characteristics (hump-free s ub-threshold) and reduce the threshold voltage variation. The basic el ements of dry-etching-assisted planarization are to locally form oxide mesas using a highly selective dry etching, and to minimize the amoun t of CMP simply by removing the locally formed oxide mesas. This new d ry-etching-assisted CMP planarization significantly reduces dishing in the large field area and improves the flatness between the high and l ow pattern density areas such as the cell array and periphery region i n a high-density DRAM.